NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 1266 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1266 of 1269NXP Semiconductors UM10503Chapter 50: Supplementary information42.7.1 C_CAN controller state after reset . . . . . . . 109242.7.2 C_CAN operating modes . . . . . . . . . . . . . . 109342.7.2.1 Software initialization . . . . . . . . . . . . . . . . . 109342.7.2.2 CAN message transfer . . . . . . . . . . . . . . . . 109342.7.2.3 Disabled Automatic Retransmission (DAR) 109442.7.2.4 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . 109442.7.2.4.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . 109442.7.2.4.2 Loop-back mode. . . . . . . . . . . . . . . . . . . . . 109542.7.2.4.3 Loop-back mode combined withSilent mode. . . . . . . . . . . . . . . . . . . . . . . . . 109542.7.2.4.4 Basic mode. . . . . . . . . . . . . . . . . . . . . . . . . 109642.7.2.4.5 Software control of pin CAN_TD . . . . . . . . 109642.7.3 CAN message handler . . . . . . . . . . . . . . . 109742.7.3.1 Management of message objects. . . . . . . . 109842.7.3.2 Data Transfer between IFx Registers and theMessage RAM . . . . . . . . . . . . . . . . . . . . . . 109942.7.3.3 Transmission of messages between the shiftregisters in the CAN core and the Messagebuffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109942.7.3.4 Acceptance filtering of received messages 109942.7.3.4.1 Reception of a data frame . . . . . . . . . . . . . . 110042.7.3.4.2 Reception of a remote frame . . . . . . . . . . . . 110042.7.3.5 Receive/transmit priority . . . . . . . . . . . . . . . 110042.7.3.6 Configuration of a transmit object . . . . . . . . 110042.7.3.7 Updating a transmit object . . . . . . . . . . . . . . 110142.7.3.8 Configuration of a receive object . . . . . . . . . 110142.7.3.9 Handling of received messages. . . . . . . . . . 110242.7.3.10 Configuration of a FIFO buffer . . . . . . . . . . . 110342.7.3.10.1 Reception of messages with FIFO buffers. 110342.7.3.10.2 Reading from a FIFO buffer . . . . . . . . . . . . 110342.7.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . 110442.7.5 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110542.7.5.1 Bit time and bit rate . . . . . . . . . . . . . . . . . . . 1106Chapter 43: LPC43xx I2C-bus interface43.1 How to read this chapter . . . . . . . . . . . . . . . 110843.2 Basic configuration . . . . . . . . . . . . . . . . . . . 110843.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110843.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . 110943.5 General description . . . . . . . . . . . . . . . . . . . 110943.5.1 I 2C Fast-mode Plus . . . . . . . . . . . . . . . . . . 111043.6 Pin description . . . . . . . . . . . . . . . . . . . . . . . 111043.7 Register description . . . . . . . . . . . . . . . . . . 111043.7.1 I 2C Control Set register. . . . . . . . . . . . . . . . 111343.7.2 I 2C Status register. . . . . . . . . . . . . . . . . . . . 111543.7.3 I 2C Data register . . . . . . . . . . . . . . . . . . . . 111543.7.4 I 2C Slave Address register 0 . . . . . . . . . . . 111543.7.5 I 2C SCL HIGH and LOW duty cycleregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . 111643.7.5.1 Selecting the appropriate I 2 C data rate and dutycycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111643.7.6 I 2C Control Clear register . . . . . . . . . . . . . 111743.7.7 I 2C Monitor mode control register. . . . . . . . 111743.7.7.1 Interrupt in Monitor mode . . . . . . . . . . . . . . 111843.7.7.2 Loss of arbitration in Monitor mode . . . . . . 111943.7.8 I 2C Slave Address registers . . . . . . . . . . . . 111943.7.9 I 2C Data buffer register . . . . . . . . . . . . . . . . 111943.7.10 I 2C Mask registers . . . . . . . . . . . . . . . . . . . 112043.8 I2 C operating modes . . . . . . . . . . . . . . . . . . 112043.8.1 Master Transmitter mode . . . . . . . . . . . . . . 112143.8.2 Master Receiver mode . . . . . . . . . . . . . . . . 112243.8.3 Slave Receiver mode . . . . . . . . . . . . . . . . . 112243.8.4 Slave Transmitter mode . . . . . . . . . . . . . . . 112343.9 I2 C implementation and operation . . . . . . . 112443.9.1 Input filters and output stages. . . . . . . . . . . 112543.9.2 Address Registers, ADR0 to ADR3 . . . . . . 112643.9.3 Address mask registers, MASK0 to MASK3 112643.9.4 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . 112643.9.5 Shift register, DAT. . . . . . . . . . . . . . . . . . . . 112643.9.6 Arbitration and synchronization logic . . . . . 112643.9.7 Serial clock generator . . . . . . . . . . . . . . . . . 112743.9.8 Timing and control . . . . . . . . . . . . . . . . . . . 112843.9.9 Control register, CONSET and CONCLR . . 112843.9.10 Status decoder and status register. . . . . . . . 112843.10 Details of I2 C operating modes . . . . . . . . . . 112843.10.1 Master Transmitter mode . . . . . . . . . . . . . . . 112943.10.2 Master Receiver mode. . . . . . . . . . . . . . . . . 113343.10.3 Slave Receiver mode. . . . . . . . . . . . . . . . . . 113643.10.4 Slave Transmitter mode . . . . . . . . . . . . . . . . 114043.10.5 Miscellaneous states . . . . . . . . . . . . . . . . . . 114243.10.5.1 STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . . 114243.10.5.2 STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . . 114243.10.6 Some special cases . . . . . . . . . . . . . . . . . . . 114343.10.6.1 Simultaneous Repeated START conditions fromtwo masters . . . . . . . . . . . . . . . . . . . . . . . . . 114343.10.6.2 Data transfer after loss of arbitration . . . . . . 114443.10.6.3 Forced access to the I 2C-bus. . . . . . . . . . . . 114443.10.6.4 I 2C-bus obstructed by a LOW level on SCL orSDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114543.10.6.5 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 114543.10.7 I 2C state service routines . . . . . . . . . . . . . . . 114543.10.8 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 114643.10.9 I 2C interrupt service . . . . . . . . . . . . . . . . . . . 114643.10.10 The state service routines . . . . . . . . . . . . . . 114643.10.11 Adapting state services to an application. . . 114643.11 Software example . . . . . . . . . . . . . . . . . . . . . 114643.11.1 Initialization routine . . . . . . . . . . . . . . . . . . . 114643.11.2 Start Master Transmit function . . . . . . . . . . . 114643.11.3 Start Master Receive function . . . . . . . . . . . 114743.11.4 I 2C interrupt routine . . . . . . . . . . . . . . . . . . . 114743.11.5 Non mode specific states. . . . . . . . . . . . . . . 114743.11.5.1 State: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 114743.11.5.2 Master States . . . . . . . . . . . . . . . . . . . . . . . . 114743.11.5.3 State: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 114743.11.5.4 State: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 114843.11.6 Master Transmitter states . . . . . . . . . . . . . . 114843.11.6.1 State: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 114843.11.6.2 State: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 114843.11.6.3 State: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 114843.11.6.4 State: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 1149

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