NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 138 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 138 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)48 18.432 368.64 0 63 2665 14 0x00000a69 0x0003f00e44.1 16.9344 338.688 0 45 18810 14 0x0000497a 0x0002d00e32 12.288 368.64 0 63 2665 24 0x00000a69 0x0003f01824 9.216 460.8 0 5 12733 6 0x000031bd 0x0000500622.05 8.4672 423.36 0 63 17692 6 0x0000451c 0x0003f00616 6.144 307.2 0 5 30580 6 0x00007774 0x0000500612 4.608 276.48 0 63 1513 18 0x000005e9 0x0003f012512 Fs192 98.304 393.216 0 45 10784 66 0x00002a20 0x0002d04296 49.152 491.52 0 63 13523 5 0x000034d3 0x0003f00588.2 45.1584 451.584 0 45 29122 5 0x000071c2 0x0002d00564 32.768 327.68 0 102 7482 5 0x00001d3a 0x0006600548 24.576 491.52 0 63 13523 14 0x000034d3 0x0003f00e44.1 22.5792 451.584 0 45 29122 14 0x000071c2 0x0002d00e32 16.384 491.52 0 63 13523 24 0x000034d3 0x0003f01824 12.288 368.64 0 63 2665 24 0x00000a69 0x0003f01822.05 11.2896 338.688 0 45 18810 24 0x0000497a 0x0002d01816 8.192 409.6 0 61 18724 6 0x00004924 0x0003d00612 6.144 307.2 0 5 30580 6 0x00007774 0x0000500611.025 5.6448 282.24 0 63 31356 6 0x00007a7c 0x0003f0061024 Fs192 196.608 393.216 0 45 10784 98 0x00002a20 0x0002d06296 98.304 393.216 0 45 10784 66 0x00002a20 0x0002d04288.2 90.3168 541.901 31 181 3535 1 0x00000dcf 0x000b500164 65.536 393.216 0 45 10784 1 0x00002a20 0x0002d00148 49.152 491.52 0 63 13523 5 0x000034d3 0x0003f00544.1 45.1584 451.584 0 45 29122 5 0x000071c2 0x0002d00532 32.768 327.68 0 102 7482 5 0x00001d3a 0x0006600524 24.576 491.52 0 63 13523 14 0x000034d3 0x0003f00e22.05 22.5792 451.584 0 45 29122 14 0x000071c2 0x0002d00e16 16.384 491.52 0 63 13523 24 0x000034d3 0x0003f01812 12.288 368.64 0 63 2665 24 0x00000a69 0x0003f01811.025 11.2896 338.688 0 45 18810 24 0x0000497a 0x0002d0188 8.192 409.6 0 61 18724 6 0x00004924 0x0003d006Table 96. PLL0AUDIO divider setting for 12 MHz with fractional divider bypassedFs[KHz]Fout[MHz]Fcco[MHz]Error[Hz] NDEC MDEC PDECPLL0AUDIO_MDIVPLL0AUDIO_NP_DIVTable 76 Table 77