UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 238 of 1269NXP Semiconductors UM10503Chapter 14: LPC43xx Pin configurationP2_6 K16 J14 137 [3] N;PUI/O SGPIO7 — General purpose digital input/output pin.I/O U0_DIR — RS-485/EIA-485 output enable/direction control forUSART0.I/O EMC_A10 — External memory address line 10.O USB0_IND0 — USB0 port indicator LED controloutput 0.I/O GPIO5[6] — General purpose digital input/output pin.I CTIN_7 — SCT input 7.I T3_CAP3 — Capture input 3 of timer 3.O EMC_BLS1 — LOW active Byte Lane select signal 1.P2_7 H14 G12 138 [3] N;PUI/O GPIO0[7] — General purpose digital input/output pin. If this pin ispulled LOW at reset, the part enters ISP mode or boots from anexternal source (see Table 18 and Table 19).O CTOUT_1 — SCT output 1. Match output 3 of timer 3.I/O U3_UCLK — Serial clock input/output for USART3 in synchronousmode.I/O EMC_A9 — External memory address line 9.- R — Function reserved.- R — Function reserved.O T3_MAT3 — Match output 3 of timer 3.- R — Function reserved.P2_8 J16 H14 140 [3] N;PUI/O SGPIO15 — General purpose digital input/output pin. Boot pin (seeTable 19).O CTOUT_0 — SCT output 0. Match output 0 of timer 0.I/O U3_DIR — RS-485/EIA-485 output enable/direction control forUSART3.I/O EMC_A8 — External memory address line 8.I/O GPIO5[7] — General purpose digital input/output pin.- R — Function reserved.- R — Function reserved.- R — Function reserved.P2_9 H16 G14 144 [3] N;PUI/O GPIO1[10] — General purpose digital input/output pin. Boot pin (seeTable 19).O CTOUT_3 — SCT output 3. Match output 3 of timer 0.I/O U3_BAUD — Baud pin for USART3.I/O EMC_A0 — External memory address line 0.- R — Function reserved.- R — Function reserved.- R — Function reserved.- R — Function reserved.Table 130. LPC4357/53 Pin description …continuedPin nameLBGA256TFBGA180LQFP208Reset state[2]TypeDescription