NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 554 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 554 of 1269NXP Semiconductors UM10503Chapter 23: LPC43xx USB0 Host/Device/OTG controller• Software writes a ‘1’ to the port reset bit in the PORTSC1 register to reset the device.• Software writes a ‘0’ to the port reset bit in the PORTSC1 register after 10 ms.This step, which is necessary in a standard EHCI design, may be omitted with thisimplementation. Should the EHCI host controller driver attempt to write a ‘0’ to theport reset bit while a reset is in progress, the write will simply be ignored, and the resetwill continue until completion.• [Port Change Interrupt] Port enable change occurs to notify the host controller thatthe device is now operational, and at this point the port speed has been determined.23.8.3.1.2 Port speed detectionAfter the port change interrupt indicates that a port is enabled, the EHCI stack shoulddetermine the port speed. Unlike the EHCI implementation which will re-assign the portowner for any device that does not connect at High-Speed, this host controller supportsdirect-attach of non High-Speed devices. Therefore, the following differences areimportant regarding port speed detection:• Port Owner is read-only and always reads 0.• A 2-bit Port Speed indicator has been added to the PORTSC1register to provide thecurrent operating speed of the port to the host controller driver.• A 1-bit High Speed indicator has been added to the PORTSC1register to indicate thatthe port is in High-Speed vs. Full/Low Speed – This information is redundant with the2-bit Port Speed indicator above.23.9 Device data structuresThis section defines the interface data structures used to communicate control, status,and data between Device Controller Driver (DCD) Software and the device controller. Thedata structure definitions in this chapter support a 32-bit memory buffer address space.Remark: The software must ensure that no interface data structure reachable by theDevice controller crosses a 4kB-page boundary.The data structures defined in the chapter are (from the device controller’s perspective) amix of read-only and read/ writable fields. The DCD must preserve the read-only fields onall data structure writes.