NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 625 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 625 of 1269NXP Semiconductors UM10503Chapter 24: LPC43xx USB1 Host/Device controller[1] There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In mostsystems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set afterwriting a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking theassociated ENDPTSETUPSTAT bit.24.6.23 Endpoint 1 to 3 control registersEach endpoint that is not a control endpoint has its own register to set the endpoint typeand enable or disable the endpoint.Remark: The reset value for all endpoint types is the control endpoint. If one endpointdirection is enabled and the paired endpoint of opposite direction is disabled, then theendpoint type of the unused direction must be changed from the control type to any othertype (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behaviorfor the data PID tracking on the active endpoint.16 TXS Tx endpoint stall R/W0 Endpoint ok.1 Endpoint stalledSoftware can write a one to this bit to force the endpoint to return aSTALL handshake to the Host. It will continue returning STALL untilthe bit is cleared by software, or it will automatically be cleared uponreceipt of a new SETUP request.After receiving a SETUP request, this bit will continue to be clearedby hardware until the associated ENDSETUPSTAT bit is cleared.[1]17 - - Reserved19:18 TXT 0x0 Endpoint typeEndpoint 0 is always a control endpoint.0 RO22:20 - - Reserved23 TXE 1 Tx endpoint enableEndpoint enabled. Control endpoint 0 is always enabled. This bit isalways 1.1 RO31:24 - - ReservedTable 491. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description …continuedBit Symbol Value Description ResetvalueAccessTable 492. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to0x4000 71CC (ENDPTCTRL3)) bit descriptionBit Symbol Value Description ResetvalueAccess0 RXS Rx endpoint stall 0 R/W0 Endpoint ok.This bit will be cleared automatically upon receipt of a SETUPrequest if this Endpoint is configured as a Control Endpoint and thisbit will continue to be cleared by hardware until the associatedENDPTSETUPSTAT bit is cleared.1 Endpoint stalledSoftware can write a one to this bit to force the endpoint to return aSTALL handshake to the Host. It will continue returning STALL untilthe bit is cleared by software, or it will automatically be cleared uponreceipt of a new SETUP request.[1]