NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1204 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1204 of 1269NXP Semiconductors UM10503Chapter 47: LPC43xx EEPROM memory47.5.2 Interrupt registersThese registers control interrupts from the EEPROM.47.5.2.1 Interrupt enable clear register47.5.2.2 Interrupt enable set register47.5.2.3 Interrupt status registerTable 1073.Interrupt enable clear register (INTENCLR - address 0x4000 EFD8) bit descriptionBits Symbol Description Reset value1:0 - Reserved. Read value is undefined, only zero should be written. NA2 PROG_CLR_EN Clear program operation finished interrupt enable bit for EEPROM.0 = leave corresponding bit unchanged.1 = clear corresponding bit.031:3 - Reserved. Read value is undefined, only zero should be written. NATable 1074.Interrupt enable set register (INTENSET - address 0x4000 EFDC) bit descriptionBits Symbol Description Reset value1:0 - Reserved. Read value is undefined, only zero should be written. NA2 PROG_SET_EN Set program operation finished interrupt enable bit for EEPROM device 1.0 = leave corresponding bit unchanged.1 = set corresponding bit.031:3 - Reserved. Read value is undefined, only zero should be written. NATable 1075.Interrupt status register (INTSTAT - address 0x4000 EFE0) bit descriptionBits Symbol Description Resetvalue1:0 - Reserved. The value read from a reserved bit is not defined. NA2 END_OF_PROG EEPROM program operation finished interrupt status bit.Bit is:- set when this operation has finished OR when one is written to the corresponding bitof the INTSTATSET register.- cleared when one is written to the corresponding bit of the INTSTATCLR register.031:3 - Reserved. The value read from a reserved bit is not defined. NA