NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 586 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 586 of 126924.1 How to read this chapterThe USB1 Host/Device controller is available on parts LPC435x and LPC433x.USB frame length adjustment is available for parts with on-chip flash only.24.2 Basic configurationThe USB1 controller is configured as follows:• See Table 451 for clocking and power control.• The USB1 is reset by a USB1_RST (reset # 18).• The USB1 interrupt is connected to interrupt slot # 9 in the NVIC. The USBAHB_NEED_CLK signal is connected to slot # 10 in the event router. (SeeSection 24.7.1).• In the SFSUSB register, the USB_ESEA bit must be set to 1 for the USB1 to operate(see Table 136).• The registers for frame length adjustment in USB host mode are located in the CREGblock (see Table 56; parts with on-chip flash only).24.2.1 Full-speed mode without external PHYIn Full-speed mode, use CLK_USB1 to generate a clock for the USB1 interface.24.2.2 High-speed mode with ULPI interfaceIn High-speed mode, the external PHY generates the clock for the USB1 interface, andthe USB1_ULPI_CLK must be enabled on pins PC_0 or P8_8 through their respective pinconfiguration registers in the system configuration block. The USB1 branch clockCLK_USB1 must be disabled.24.3 Features• Supports all high-speed USB-compliant peripherals if connected to external ULPIPHY.UM10503Chapter 24: LPC43xx USB1 Host/Device controllerRev. 1.3 — 6 July 2012 User manualTable 451. USB1 clocking and power controlBase clock Branch clock OperatingfrequencyNotesUSB1 clock BASE_USB1_CLK CLK_USB1 60 MHz Uses PLL1. CLK_USB1 mustbe 60 MHz when the USB1 isoperated in low-speed andfull-speed modes. Inhigh-speed mode, the clockis provided by the ULPI PHY.USB1 registerinterface clockBASE_M4_CLK CLK_M4_USB1 up to204 MHz