NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 346 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 346 of 1269NXP Semiconductors UM10503Chapter 17: LPC43xx GPIOApplications in which interrupts can result in Masked GPIO operation, or in task switchingamong tasks that do Masked GPIO operation, must treat code that uses the Mask registeras a protected/restricted region. This can be done by interrupt disabling or by using asemaphore.The simpler way to protect a block of code that uses a MASK register is to disableinterrupts before setting the MASK register, and re-enable them after the last operationthat uses the MPORT or MASK register.More efficiently, software can dedicate a semaphore to the MASK registers, andset/capture the semaphore controlling exclusive use of the MASK registers before settingthe MASK registers, and release the semaphore after the last operation that uses theMPORT or MASK registers.17.6.4 GPIO InterruptsTwo separate GPIO interrupt facilities are provided. With pin interrupts, up to eight GPIOpins can each have separately-vectored, edge- or level-sensitive interrupts.With group interrupts, any subset of the pins in each port can be selected to contribute toa common interrupt. Any of the pin and port interrupts can be enabled in the NVIC to wakethe part from Sleep mode.17.6.4.1 Pin interruptsIn this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin InterruptSelect registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits,corresponding to the pins called out by the PINTSEL0-7 registers. The ISEL registerdefines whether each interrupt pin is edge- or level-sensitive. The RISE and FALLregisters detect edges on each interrupt pin, and can be written to clear (and set) edgedetection. The IST register indicates whether each interrupt pin is currently requesting aninterrupt, and this register can also be written to clear interrupts.The other pin interrupt registers play different roles for edge-sensitive and level-sensitivepins, as described in Table 208.17.6.4.2 Group interruptsIn this interrupt facility, an interrupt can be requested for each port, based on any selectedsubset of pins within each port. The pins that contribute to each port interrupt are selectedby 1s in the port’s Enable register, and an interrupt polarity can be selected for each pin inthe port’s Polarity register. The level on each pin is exclusive-ORed with its polarity bit andthe result is ANDed with its enable bit, and these results are then inclusive-ORed amongall the pins in the port, to create the port’s raw interrupt request.Table 208. Pin interrupt registers for edge- and level-sensitive pinsName Edge-sensitive function Level-sensitive functionIENR Enables rising-edge interrupts. Enables level interrupts.SIENR Write to enable rising-edge interrupts. Write to enable level interrupts.CIENR Write to disable rising-edge interrupts. Write to disable level interrupts.IENF Enables falling-edge interrupts. Selects active level.SIENF Write to enable falling-edge interrupts. Write to select high-active.CIENF Write to disable falling-edge interrupts. Write to select low-active.