NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1205 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1205 of 1269NXP Semiconductors UM10503Chapter 47: LPC43xx EEPROM memory47.5.2.4 Interrupt enable register47.5.2.5 Interrupt status clear register47.5.2.6 Interrupt status setTable 1076.Interrupt enable register (INTEN - address 0x4000 EFE4) bit descriptionBits Symbol Description Resetvalue1:0 - Reserved. The value read from a reserved bit is not defined. NA2 EE_PROG_DONE EEPROM program operation finished interrupt enable bit.Bit is:- set when one is written in the corresponding bit of the INTENSET register.- cleared when one is written to the corresponding bit of the INTENCLR register.031:3 - Reserved. The value read from a reserved bit is not defined. NATable 1077.Interrupt status clear register (INTSTATCLR - address 0x4000 EFE8) bit descriptionBits Symbol Description Reset value1:0 - Reserved. Read value is undefined, only zero should be written. NA2 PROG_CLR_ST Clear program operation finished interrupt status bit for EEPROM device.0 = leave corresponding bit unchanged.1 = clear corresponding bit.031:3 - Reserved. Read value is undefined, only zero should be written. NATable 1078.Interrupt status set register (INTSTATSET - address 0x4000 EFEC)Bits Symbol Description Reset value1:0 - Reserved. Read value is undefined, only zero should be written. NA2 PROG_SET_ST Set program operation finished interrupt status bit for EEPROM device.0 = leave corresponding bit unchanged.1 = set corresponding bit.031:3 - Reserved. Read value is undefined, only zero should be written. NA