NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 1264 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1264 of 1269NXP Semiconductors UM10503Chapter 50: Supplementary informationRS-485/EIA-485 Auto Address Detection (AAD)mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .976RS-485/EIA-485 Auto Direction Control . . . . .976RS485/EIA-485 driver delay time . . . . . . . . . .977RS485/EIA-485 output inversion . . . . . . . . . .97737.7.5 Synchronous mode. . . . . . . . . . . . . . . . . . . . 97737.7.5.1 Synchronous slave mode. . . . . . . . . . . . . . . 977Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . 977Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 97837.7.5.2 Synchronous master mode . . . . . . . . . . . . . 97837.7.6 Smart card mode . . . . . . . . . . . . . . . . . . . . . 97937.7.6.1 Smart card set-up procedure . . . . . . . . . . . . 979Chapter 38: LPC43xx UART138.1 How to read this chapter . . . . . . . . . . . . . . . . 98138.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 98138.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98138.4 General description . . . . . . . . . . . . . . . . . . . . 98138.5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 98438.6 Register description . . . . . . . . . . . . . . . . . . . 98538.6.1 UART1 Receiver Buffer Register (whenDLAB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98638.6.2 UART1 Transmitter Holding Register (whenDLAB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98638.6.3 UART1 Divisor Latch LSB and MSB Registers(when DLAB = 1) . . . . . . . . . . . . . . . . . . . . . 98638.6.4 UART1 Interrupt Enable Register (whenDLAB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98738.6.5 UART1 Interrupt Identification Register . . . . 98838.6.6 UART1 FIFO Control Register . . . . . . . . . . . 99038.6.6.1 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 991UART receiver DMA . . . . . . . . . . . . . . . . . . . .991UART transmitter DMA . . . . . . . . . . . . . . . . . .99138.6.7 UART1 Line Control Register . . . . . . . . . . . 99138.6.8 UART1 Modem Control Register . . . . . . . . 99238.6.9 UART1 Line Status Register . . . . . . . . . . . . 99338.6.10 UART1 Modem Status Register . . . . . . . . . 99538.6.11 UART1 Scratch Pad Register . . . . . . . . . . . 99538.6.12 UART1 Auto-baud Control Register . . . . . . 99538.6.13 UART1 Fractional Divider Register . . . . . . . 99638.6.14 UART1 Transmit Enable Register . . . . . . . . 99738.6.15 UART1 RS485 Control register . . . . . . . . . . 99838.6.16 UART1 RS-485 Address Match register . . . 99938.6.17 UART1 RS-485 Delay value register . . . . . 99938.7 Functional description . . . . . . . . . . . . . . . . . 99938.7.1 Auto-flow control . . . . . . . . . . . . . . . . . . . . . 99938.7.1.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 99938.7.1.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . 100038.7.2 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . 100138.7.3 Auto-baud modes. . . . . . . . . . . . . . . . . . . . 100138.7.4 Baud rate calculation . . . . . . . . . . . . . . . . . 100138.7.5 RS-485/EIA-485 modes of operation . . . . . 1001Chapter 39: LPC43xx SSP0/139.1 How to read this chapter . . . . . . . . . . . . . . . 100239.2 Basic configuration . . . . . . . . . . . . . . . . . . . 100239.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100239.4 General description . . . . . . . . . . . . . . . . . . . 100239.5 Pin description . . . . . . . . . . . . . . . . . . . . . . . 100339.6 Register description . . . . . . . . . . . . . . . . . . 100339.6.1 SSP Control Register 0 . . . . . . . . . . . . . . . 100439.6.2 SSP Control Register 1 . . . . . . . . . . . . . . . 100539.6.3 SSP Data Register . . . . . . . . . . . . . . . . . . . 100639.6.4 SSP Status Register . . . . . . . . . . . . . . . . . 100739.6.5 SSP Clock Prescale Register . . . . . . . . . . 100739.6.6 SSP Interrupt Mask Set/Clear Register . . . 100739.6.7 SSP Raw Interrupt Status Register . . . . . . 100839.6.8 SSP Masked Interrupt Status Register . . . 100839.6.9 SSP Interrupt Clear Register . . . . . . . . . . . 100939.6.10 SSP DMA Control Register . . . . . . . . . . . . 100939.7 Functional description . . . . . . . . . . . . . . . . 101039.7.1 Texas Instruments synchronous serial frameformat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101039.7.2 SPI frame format . . . . . . . . . . . . . . . . . . . . . 101139.7.2.1 Clock Polarity (CPOL) and Phase (CPHA)control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101139.7.2.2 SPI format with CPOL=0,CPHA=0. . . . . . . . 101139.7.2.3 SPI format with CPOL=0,CPHA=1. . . . . . . 101239.7.2.4 SPI format with CPOL = 1,CPHA = 0. . . . . 101339.7.2.5 SPI format with CPOL = 1,CPHA = 1. . . . . 101439.7.3 National Semiconductor Microwire frameformat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101539.7.3.1 Setup and hold time requirements on CS withrespect to SK in Microwire mode . . . . . . . . 1016Chapter 40: LPC43xx SPI40.1 How to read this chapter . . . . . . . . . . . . . . . 101740.2 Basic configuration . . . . . . . . . . . . . . . . . . . 101740.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101740.4 General description . . . . . . . . . . . . . . . . . . . 101740.5 Pin description . . . . . . . . . . . . . . . . . . . . . . . 101940.6 Register description . . . . . . . . . . . . . . . . . . 101940.6.1 SPI Control Register . . . . . . . . . . . . . . . . . 102040.6.2 SPI Status Register . . . . . . . . . . . . . . . . . . 102140.6.3 SPI Data Register . . . . . . . . . . . . . . . . . . . 102240.6.4 SPI Clock Counter Register . . . . . . . . . . . 102240.6.5 SPI Test Control Register . . . . . . . . . . . . . 102340.6.6 SPI Test Status Register . . . . . . . . . . . . . . 102340.6.7 SPI Interrupt Register . . . . . . . . . . . . . . . . 102340.7 Functional description . . . . . . . . . . . . . . . . 102440.7.1 SPI data transfers . . . . . . . . . . . . . . . . . . . 1024