NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1160 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1160 of 1269NXP Semiconductors UM10503Chapter 44: LPC43xx 10-bit ADC0/144.6.2 A/D Global Data registerThe A/D Global Data Register contains the result of the most recent A/D conversion whenthe ADC operates in software-controlled, non-burst mode (BURST bit set to zero andSTART bits set to 0x1 in the CR register). This includes the data, DONE, and Overrunflags, and the number of the A/D channel to which the data relates.Remark: Use only the individual channel data registers DR0 to DR7 with burst mode orwith hardware triggering to read the conversion results.44.6.3 A/D Interrupt Enable registerThis register allows control over which A/D channels generate an interrupt when aconversion is complete. For example, it may be desirable to use some A/D channels tomonitor sensors by continuously performing conversions on them. The most recentresults are read by the application program whenever they are needed. In this case, aninterrupt is not desirable at the end of each conversion for some A/D channels.Table 1011.A/D Global Data register (GDR - address 0x400E 3004 (ADC0) and 0x400E 4004(ADC1)) bit descriptionBit Symbol Description Resetvalue5:0 - Reserved. These bits always read as zeroes. 015:6 V_VREF When DONE is 1, this field contains a binary fraction representingthe voltage on the ADCn pin selected by the SEL field, divided bythe reference voltage on the VDDA pin. Zero in the field indicatesthat the voltage on the ADCn input pin was less than, equal to, orclose to that on VSSA, while 0x3FF indicates that the voltage onADCn input pin was close to, equal to, or greater than that onVDDA.-23:16 - Reserved. These bits always read as zeroes. 026:24 CHN These bits contain the channel from which the LS bits wereconverted.-29:27 - Reserved. These bits always read as zeroes. 030 OVERRUN This bit is 1 in burst mode if the results of one or more conversionswas (were) lost and overwritten before the conversion thatproduced the result in the V_VREF bits.031 DONE This bit is set to 1 when an analog-to-digital conversion completes.It is cleared when this register is read and when the AD0/1CRregister is written. If the AD0/1CR is written while a conversion isstill in progress, this bit is set and a new conversion is started.0