NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1035 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1035 of 1269NXP Semiconductors UM10503Chapter 41: LPC43xx I2S interface41.6.1 I2S Digital Audio Output registerThe DAO register controls the operation of the I2S transmit channel. The function of bits inDAO are shown in Table 898.Table 897. Register overview: I2S1 (base address 0x400A 3000)Name Access AddressoffsetDescription ResetvalueReferenceDAO R/W 0x000 I2S Digital Audio Output Register. Contains control bits forthe I2S transmit channel.0x87E1 Table 898DAI R/W 0x004 I2S Digital Audio Input Register. Contains control bits forthe I2S receive channel.0x07E1 Table 899TXFIFO WO 0x008 I2S Transmit FIFO. Access register for the 8 x 32-bittransmitter FIFO.0 Table 900RXFIFO RO 0x00C I2S Receive FIFO. Access register for the 8 x 32-bitreceiver FIFO.0 Table 901STATE RO 0x010 I2S Status Feedback Register. Contains status informationabout the I2S interface.0x7 Table 902DMA1 R/W 0x014 I2S DMA Configuration Register 1. Contains controlinformation for DMA request 1.0 Table 903DMA2 R/W 0x018 I2S DMA Configuration Register 2. Contains controlinformation for DMA request 2.0 Table 904IRQ R/W 0x01C I2S Interrupt Request Control Register. Contains bits thatcontrol how the I2S interrupt request is generated.0 Table 905TXRATE R/W 0x020 I2S Transmit MCLK divider. This register determines theI2S TX MCLK rate by specifying the value to divide PCLKby in order to produce MCLK.0 Table 906RXRATE R/W 0x024 I2S Receive MCLK divider. This register determines theI2S RX MCLK rate by specifying the value to divide PCLKby in order to produce MCLK.0 Table 907TXBITRATE R/W 0x028 I2S Transmit bit rate divider. This register determines theI2S transmit bit rate by specifying the value to divideTX_MCLK by in order to produce the transmit bit clock.0 Table 908RXBITRATE R/W 0x02C I2S Receive bit rate divider. This register determines theI2S receive bit rate by specifying the value to divideRX_MCLK by in order to produce the receive bit clock.0 Table 909TXMODE R/W 0x030 I2S Transmit mode control. 0 Table 910RXMODE R/W 0x034 I2S Receive mode control. 0 Table 911Table 898. I2S Digital Audio Output register (DAO - address 0x400A 2000 (I2S0) and 0x400A 3000 (I2S1)) bitdescriptionBit Symbol Value Description Resetvalue1:0 WORDWIDTH Selects the number of bytes in data as follows: 010x0 8-bit data0x1 16-bit data0x2 Reserved, do not use this setting0x3 32-bit data2 MONO When 1, data is of monaural format. When 0, the data is in stereo format. 0