NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1092 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1092 of 1269NXP Semiconductors UM10503Chapter 42: LPC43xx C_CAN42.6.4 CAN timing register42.6.4.1 CAN clock divider registerThis register determines the CAN clock signal. The CAN_CLK is derived from theperipheral clock PCLK divided by the values in this register.42.7 Functional description42.7.1 C_CAN controller state after resetAfter a hardware reset, the registers hold the values described in Table 931. Additionally,the busoff state is reset and the output CAN_TX is set to recessive (HIGH). The value0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. TheCAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.The data stored in the message RAM is not affected by a hardware reset. After power-on,the contents of the message RAM is undefined.Table 973. CAN message valid 2 register (MSGV2, address 0x400E 2164 (C_CAN0) and0x400A 4164 (C_CAN1)) bit descriptionBit Symbol Description Access Resetvalue15:0 MSGVAL32_17 Message valid bits of message objects 32 to 17.0 = This message object is ignored by the messagehandler.1 = This message object is configured and shouldbe considered by the message handler.R 0x0031:16 - Reserved - -Table 974. CAN clock divider register (CLKDIV, address 0x400E 2180 (C_CAN0) and 0x400A4180 (C_CAN1)) bit descriptionBit Symbol Description ResetvalueAccess3:0 CLKDIVVAL Clock divider valueCAN_CLK = PCLK/(2 CLKDIVVAL -1 +1)0000: CAN_CLK = PCLK divided by 1.0001: CAN_CLK = PCLK divided by 2.0010: CAN_CLK = PCLK divided by 3.0010: CAN_CLK = PCLK divided by 4.0011: CAN_CLK = PCLK divided by 5.0100: CAN_CLK = PCLK divided by 9.0101: CAN_CLK = PCLK divided by 17....1111: CAN_CLK = PCLK divided by 16385.0001 R/W31:4 - reserved - -