NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 110 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 110 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)11.6.4.2 PLL0AUDIO control registerTable 75. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bitdescriptionBit Symbol Value Description ResetvalueAccess0 PD PLL0 power down 1 R/W0 PLL0 enabled1 PLL0 powered down1 BYPASS Input clock bypass control 1 R/W0 CCO clock sent to post-dividers. Use thisin normal operation.1 PLL0 input clock sent to post-dividers(default).2 DIRECTI PLL0 direct input 0 R/W3 DIRECTO PLL0 direct output 0 R/W4 CLKEN PLL0 clock enable 0 R/W5 - Reserved - -6 FRM Free running mode 0 R/W7 - Reserved 0 R/W8 - Reserved. Reads as zero. Do not writeone to this register.0 R/W9 - Reserved. Reads as zero. Do not writeone to this register.0 R/W10 - Reserved. Reads as zero. Do not writeone to this register.0 R/W11 AUTOBLOCK Block clock automatically during frequencychange0 R/W0 Autoblocking disabled1 Autoblocking enabled12 PLLFRACT_REQFractional PLL word write request. Set thisbit to 1 if the fractional divider is enabled inthe SEL_EXT bit.0 R/W13 SEL_EXT Select fractional divider. 0 R/W0 Enable fractional divider.1 MDEC enabled. Fractional divider notused.14 MOD_PD Sigma-Delta modulator power-down 1 R/W0 Sigma-Delta modulator enabled1 Sigma-Delta modulator powered down23:15 - Reserved - -